Microarchitecture Categorization and Pre-RTL Analytical Modeling for Sparse Tensor Accelerators
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feldman-abf149-meng-eecs-2024-thesis.pdf
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Thesis PDF
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27.88 MB
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Author(s)
Feldman, Andrew
Advisor(s)
Sze, Vivienne
Erner, Joel
Date Issued
February 2024
Publisher
Massachusetts Institute of Technology
Abstract
Specialized microarchitectures for exploiting sparsity have been critical to the design of sparse tensor accelerators. Sparseloop introduced the Sparse Acceleration Feature (SAF) abstraction, which unifies prior work on sparse tensor accelerators into a taxonomy of sparsity optimizations.
Sparseloop succeeds at analytical pre-RTL modeling of architecture-level metrics for sparse tensor accelerators, accurately capturing the beneficial impact of SAFs on overall design cost. However, Sparseloop lacks cost models for microarchitectural primitives and design topologies required for implementing SAFs (referred to in this work as "SAF microarchitectures".)
Analysis of prior works shows that SAF microarchitectures may or may not constitute a significant overhead, depending on the particular design; thus it is desirable to have pre-RTL models which help anticipate SAF microarchitecture overheads.
Building on the Sparseloop SAF abstraction, this work1 attempts to synthesize a number of prior works into a concise, unified, and effective framework for doing research on SAF microarchitectures. This overall framework comprises (1) a conceptual framework which facilitates concise description and design-space exploration for SAF microarchitectures, (2) a software framework for compiling Sparseloop-style SAF descriptions into microarchitecture designs and analytical models, and (3) a component library including specific SAF microarchitecture subcomponent designs as well as RTL to support implementation.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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