Positive-bias temperature instability (PBTI) of GaN MOSFETs
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IRPS 6C5 v3 clean final.pdf
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Author(s)
Guo, Alex
del Alamo, Jesus A.
Date Issued
April 2015
Journal
Proceedings of the 2015 IEEE International Reliability Physics Symposium
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Guo, Alex, and Jesus A. del Alamo. “Positive-Bias Temperature Instability (PBTI) of GaN MOSFETs.” 2015 IEEE International Reliability Physics Symposium (April 2015).
Version
Author's final manuscript
Abstract
We have investigated the stability of the gate stack of GaN n-MOSFETs under positive gate stress. Devices with a gate dielectric that consists of pure SiO[subscript 2] or a composite SiO[subscript 2]/Al[subscript 2]O[subscript 3] bilayer were studied. Our research has targeted the evolution of threshold voltage (V[subscript T]), subthreshold swing (S) and transconductance (g[subscript m]) after positive gate voltage stress of different duration at different voltages and temperatures. We have also examined the recovery process after the stress is removed. We have observed positive V[subscript T] shift (ΔV[subscript T]) in both gate dielectrics under positive gate stress. In devices with a SiO[subscript 2] gate oxide, we have found that ΔV[subscript T] is caused by a combination of electron trapping in pre-existing oxide traps and interface trap generation. In devices with a composite SiO[subscript 2]/Al[subscript 2]O[subscript 3] gate oxide, on the other hand, ΔV[subscript T] is due to electron trapping in pre-existing oxide traps and generation of near interface oxide traps.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Microsystems Technology Laboratories
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DOI of Published Version
https://doi.org/10.1109/IRPS.2015.7112770
