A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy
Name
Daly-2009-A 6-bit, 0.2 V to 0.pdf
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1002.89 KB
Format
Adobe PDF
Checksum (MD5)
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Author(s)
Daly, Denis C.
Chandrakasan, Anantha P.
Date Issued
August 2009
Journal
IEEE Journal of Solid-State Circuits
Publisher
Institute of Electrical and Electronics Engineers
Citation
Daly, Denis C., and A.P. Chandrakasan. “A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy.” Solid-State Circuits, IEEE Journal of 44.11 (2009): 3030-3038. © 2009 IEEE
Version
Final published version
Abstract
A 6-bit highly digital flash ADC is implemented in a 0.18 mum CMOS process. The ADC operates in the subthreshold regime down to 200 mV and employs comparator redundancy and reconfigurability to improve linearity. The low-voltage sampling switch employs voltage boosting, stacking and feedback to reduce leakage. Common-mode rejection is implemented digitally via an IIR filter. The minimum FOM of the ADC is 125 fJ/conversion-step at a 0.4 V supply, where it achieves an ENOB of 5.05 at 400 kS/s. The clocked comparators' switching thresholds are adjusted through a combination of device sizing and stacking. A quadratic relationship between the amount of device stacking and the strength of an input network in the subthreshold regime is derived, demonstrating an advantage of stacking over device width scaling to adjust comparator thresholds.
Subjects
ultra-low-voltage operation
redundancy
reassignment
low-power electronics
comparators (circuits)
calibration
analog-digital conversion
ADC
MIT Department
Massachusetts Institute of Technology. Microsystems Technology Laboratories
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
http://dx.doi.org/10.1109/jssc.2009.2032699
