CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks
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JSSC2019_manuscript.pdf
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5.17 MB
Format
Adobe PDF
Checksum (MD5)
28df6674deb6d0449af9f5d9f0f4cd30
Author(s)
Biswas, Avishek
Chandrakasan, Anantha P
Date Issued
December 2018
Journal
IEEE Journal of Solid-State Circuits
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Biswas, Avishek and Anantha P. Chandrakasan. "CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks." IEEE Journal of Solid-State Circuits 54, 1 (January 2019): 217 - 230 © 2018 IEEE
Version
Author's final manuscript
Abstract
This paper presents an energy-efficient static random access memory (SRAM) with embedded dot-product computation capability, for binary-weight convolutional neural networks. A 10T bit-cell-based SRAM array is used to store the 1-b filter weights. The array implements dot-product as a weighted average of the bitline voltages, which are proportional to the digital input values. Local integrating analog-to-digital converters compute the digital convolution outputs, corresponding to each filter. We have successfully demonstrated functionality (>98% accuracy) with the 10 000 test images in the MNIST hand-written digit recognition data set, using 6-b inputs/outputs. Compared to conventional full-digital implementations using small bitwidths, we achieve similar or better energy efficiency, by reducing data transfer, due to the highly parallel in-memory analog computations.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1109/jssc.2018.2880918
