Parallel Write-Efficient Algorithms and Data Structures for Computational Geometry
Name
1805.05592.pdf
Description
Submitted version
Size
835.16 KB
Format
Adobe PDF
Checksum (MD5)
69c5d7c0567bc856730f8bacb50490ad
Author(s)
Blelloch, Guy E
Gu, Yan
Shun, Julian
Sun, Yihan
Date Issued
2018
Journal
Annual ACM Symposium on Parallelism in Algorithms and Architectures
Publisher
Association for Computing Machinery (ACM)
Version
Original manuscript
Abstract
© 2018 Association for Computing Machinery. In this paper, we design parallel write-efficient geometric algorithms that perform asymptotically fewer writes than standard algorithms for the same problem. This is motivated by emerging non-volatile memory technologies with read performance being close to that of random access memory but writes being significantly more expensive in terms of energy and latency. We design algorithms for planar Delaunay triangulation, k-d trees, and static and dynamic augmented trees. Our algorithms are designed in the recently introduced Asymmetric Nested-Parallel Model, which captures the parallel setting in which there is a small symmetric memory where reads and writes are unit cost as well as a large asymmetric memory where writes are ω times more expensive than reads. In designing these algorithms, we introduce several techniques for obtaining write-efficiency, including DAG tracing, prefix doubling, and α-labeling, which we believe will be useful for designing other parallel write-efficient algorithms.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1145/3210377.3210380
