Design-space exploration for CMOS photonic processor networks
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8BD7Ad01.pdf
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Author(s)
Stojanovic, Vladimir Marko
Joshi, Ajay J.
Batten, Christopher
Kwon, Yong-Jin
Beamer, Scott
Chen, Sun
Asanovic, Krste
Date Issued
May 2010
Journal
Proceedings of the Conference on (OFC/NFOEC) Optical Fiber Communication (OFC), collocated National Fiber Optic Engineers Conference, 2010
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
"Design-space exploration for CMOS photonic processor networks." Conference on (OFC/NFOEC) Optical Fiber Communication (OFC), collocated National Fiber Optic Engineers Conference, 2010. ©2010 IEEE
Version
Final published version
Abstract
Monolithically integrated dense WDM photonic network topologies optimized for loss and power footprint of optical components can achieve up to 4x better energy-efficiency and throughput than electrical interconnects in core-to-core, and 10x in core-to-DRAM networks.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=5465639&contentType=Conference+Publications
