Device Stack Optimization for Protonic Non-Volatile Programmable Resistors
Name
shen-deanshen-sm-eecs-2024-thesis.pdf
Description
Thesis PDF
Size
17.42 MB
Format
Adobe PDF
Checksum (MD5)
a969118db562533ed63f01f97df95251
Author(s)
Shen, Dingyu
Advisor(s)
del Alamo, Jesús A.
Date Issued
May 2024
Publisher
Massachusetts Institute of Technology
Abstract
Analog computing could alleviate computational bottlenecks in digital deep learning systems by utilizing local information processing through the physical properties of devices, such as electrochemical ion-intercalation in three-terminal devices where channel resistance is modulated by ionic exchange via an electrolyte. Previous work has demonstrated such ionic programmable resistors featuring WO₃ as the channel, phosphorous-doped SiO₂ (PSG) as the electrolyte, Pd as the gate reservoir, and protons as the ions. This thesis aimed to optimize the device stack in four directions and demonstrated a symmetric WO₃-PSG-WO₃ structure in a CMOS-compatible process, with the help of circular transfer length model (CTLM), which efficiently examines the resistance properties of WO₃. We have explored: (a) device protonation as part of the fabrication process, (b) encapsulation preventing proton depletion during device fabrication and operation, (c) contact metal optimization to replace gold with a CMOS-compatible material, (d) PSG evaluation vehicle for device performance optimization. The symmetric device combining all the stack optimizations features non-volatile and repeatable conductance modulation with voltage pulses.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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