SERenaDE: Hardware Acceleration of Cloud Serialization Frameworks
Name
zarkos-czarkos-sm-eecs-2025-thesis.pdf
Description
Thesis PDF
Size
903.76 KB
Format
Adobe PDF
Checksum (MD5)
cfcaf3e0db04ad7dc45fdd148b6a84a1
Author(s)
Zarkos, Christos V.
Advisor(s)
Delimitrou, Christina
Date Issued
May 2025
Publisher
Massachusetts Institute of Technology
Abstract
Serialization frameworks are a fundamental operation of datacenters, as they enable language- and platform-neutral communication and storage. However, software serialization faces major performance bottlenecks, resulting in a significant fraction of cloud cycles dedicated to this process. Prior work has proposed specialized hardware accelerators to address these overheads. While these proposals achieve considerable speedups, they are expensive in terms of verification, fabrication, and deployment, and often hardcode too many details about the (de)serialization framework in hardware. We propose SERenaDE, a serialization framework designed to integrate general-purpose accelerators currently deployed in datacenters in order to accelerate and offload serialization to hardware. Specifically, we repurpose the Intel In-Memory Analytics Accelerator (IAA), an accelerator engine offering fast compression, to enable fast and transparent to the user serialization and deserialization, completely removing software serialization from the execution pipeline. We evaluate our system on latest-generation production machines, both with synthetic microbenchmarks, and open-source representative fleet-wide benchmarks. Our results show comparable performance in terms of per-request latency across all types of messages, while significantly improving throughput - especially at the tail -, maintaining thread scalability and achieving high compression ratios alongside substantial speedups for larger messages. Under 95th latency percentile latency constraints SERenaDE improves serialization and deserialization throughput by 13% and 30% respectively, while achieving from 0.2x to 6.94x smaller serialized message sizes for messages of a total memory layout larger than 4KB.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
In Copyright - Educational Use Permitted
Copyright retained by author(s)
Persistent DSpace Link