Optimization of transistors for very high frequency dc-dc converters
Name
Sagneri-2009-Optimization of transistors for very high frequency dc-dc converters.pdf
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814.66 KB
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Checksum (MD5)
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Author(s)
Perreault, David J.
Sagneri, Anthony D.
Anderson, David I.
Date Issued
September 2009
Journal
IEEE Energy Conversion Congress and Exposition
Publisher
Institute of Electrical and Electronics Engineers
Citation
Sagneri, A.D., D.I. Anderson, and D.J. Perreault. “Optimization of transistors for very high frequency dc-dc converters.” Energy Conversion Congress and Exposition, 2009. ECCE 2009. IEEE. 2009. 1590-1602. © 2009, IEEE
Version
Final published version
Abstract
This document presents a method to optimize integrated LDMOS transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is developed. Device parameters are related to layout geometry and the resulting layout vs. loss tradeoffs are illustrated. A method of finding an optimal layout for a given converter application is developed and experimentally verified in a 50 MHz converter, resulting in a 35% reduction in power loss over an un-optimized device. It is further demonstrated that hot-carrier limits on device safe operating area may be relaxed under soft switching, yielding significant further loss reduction. A device fabricated with 20-V design rules is validated at 35-V, offering reduced parasitic resistance and capacitance. Compared to the original design, loss is up to 75% lower in the example application.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Laboratory for Electromagnetic and Electronic Systems
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/ECCE.2009.5316121
