A high-speed cascaded folding and interpolating A/D converter
Name
53843151-MIT.pdf
Description
Full printable version
Size
2.71 MB
Format
Adobe PDF
Checksum (MD5)
92625cb2c01d9cf4c627fdf47ceb90df
Author(s)
Lau, Yanlok Charlotte, 1979-
Advisor(s)
William Yang and James K. Roberge.
Date Issued
2003
Publisher
Massachusetts Institute of Technology
Abstract
The folding and interpolating technique has been introduced to CMOS analog-to- digital converter (ADC) in the 1980's. It has successfully reduced the number of comparators required while preserving the benefits of a flash ADC. However, similar to flash ADC, folding and interpolating ADC is also limited to low resolution, due to its complication in the folding operation. Cascaded folding and interpolating architecture is then adopted to alleviate the problem. The design of a 10-bit, 55MSPS ADC is presented to illustrate the merits of the architecture. Data conversion is conducted in two parallel blocks, the MSB and LSB sections. The MSB section is responsible for computing the four MSBs while the LSB section computes the remaining six LSBs. The folding and interpolation preprocessing, completed in three cascaded stages, is employed in the LSB section. The circuit functions are designed in 0.35[mu]m CMOS process with a 3.3V supply. The analog circuitry dissipates 54m W while achieving < 1 /2 LSB DNL performance in simulation.
Description
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 85-86).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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