A 16-bit, 100kS/s self-calibrating cyclic analog-to-digital converter
Name
46842214-MIT.pdf
Description
Full printable version
Size
2 MB
Format
Adobe PDF
Checksum (MD5)
2447eb8ac772dcd1ab235ac2ffa111c1
Author(s)
Guidry, Michael J. (Michael James), 1976-
Advisor(s)
Hae-Seung Lee.
Date Issued
2000
Publisher
Massachusetts Institute of Technology
Abstract
Self-calibrating AID architectures minimize the sometimes expensive process of in-factory calibration, thus allowing manufacturers to reduce chip cost. This thesis presents an AID converter built using one such architecture, the reference-refreshing architecture. This converter shows under simulation 100 kHz performance at 16 bits, with INL of 1.2 LSBs, SNR of 89 dB, and power consumption of 170 mW.
Description
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
Includes bibliographical references (leaf 50).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Persistent DSpace Link
