Design and performance evaluation of a low-power data-line SRAM sense amplifier
Name
Fu-2009-Design and performance evaluation of a low-power data-line SRAM sense amplifier.pdf
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376.42 KB
Format
Adobe PDF
Checksum (MD5)
d3405860a13c8839cd8a23d0036e7902
Author(s)
Fu, Haitao
Yeo, Kiat-Seng
Do, Anh-Tuan
Kong, Zhi-Hui
Date Issued
February 2010
Journal
Proceedings of the 2009 12th International Symposium on Integrated Circuits, ISIC '09
Publisher
Institute of Electrical and Electronics Engineers
Citation
Fu, Haitao, Kiat-Seng Yeo, Anh-Tuan Do, and Zhi-Hui Kong (2010). "Design and performance evaluation of a low-power data-line SRAM sense amplifier." Proceedings of the 2009 12th International Symposium on Integrated Circuits, ISIC'09 (Piscataway, N.J.: IEEE): 291-294. © 2010 IEEE
Version
Final published version
Abstract
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. The heavy bit-and data-line capacitances are the major road blocks to its performance. A high-performance SRAM is proposed using a 1.8 V/0.18 à ¿m CMOS standard process from Chartered Semiconductor Manufacturing Ltd (CHRT). It incorporates a discharging mechanism that helps eliminating the waiting time during the read operation, hence offering a faster sensing speed and lower power consumption. Our post-layout simulation results have shown that it improves the sensing speed and power consumption by 51.4%, and 62.47%, respectively when compared with the best published design. The total power-delay-product (PDP) is 81.79% better. Furthermore, it can operate at a supply voltage as low as 0.8 V with a high stability to the bit-line capacitances variation and mismatch.
Subjects
CMOS integrated circuits
SRAM chips
amplifiers
cache storage
logic design
low-power electronics
system-on-chip
CHRT
CMOS standard process
Chartered Semiconductor Manufacturing Ltd.
bit-line capacitances variation
data-line capacitances
discharging mechanism
electronic industry
low-power data-line SRAM sense amplifier evaluation
lower power consumption
post-layout simulation
size 0.18 mum
total power-delay-product
voltage 1.8 V
MIT Department
Massachusetts Institute of Technology. Department of Materials Science and Engineering
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
Persistent DSpace Link
DOI of Published Version
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5403784
