Variation-aware placement tool for Field Programmable Gate Array devices
Name
220913621-MIT.pdf
Description
Full printable version
Size
6.22 MB
Format
Adobe PDF
Checksum (MD5)
6aef33a88847def1be80264c2de0ec20
Author(s)
Perez, Christopher E
Advisor(s)
Arif Rahman and Charles G. Sodini.
Alternative Title
process variation-aware placement tool for FGPA devices
Date Issued
2007
Publisher
Massachusetts Institute of Technology
Abstract
Introduction: As semiconductor technologies become more advanced, process variations within microelectronic devices, including variations in channel length or in oxide thickness, play a much more important role with regards to circuit delay and leakage power dissipation. These process variations cause variability in circuit performance characteristics that can be minimized by improving process control techniques, resulting in more predictable behavior. However, if we are concerned with programmable logic devices like FPGAs affected by variation, the circuit designer in the field has no control over or knowledge about the manner in which process variations affect the device and the final circuit implementation. Our research here is aimed at developing and incorporating process variation models into circuit design and implementation tools for FPGAs. With variation aware tools, programmable logic device users will have the opportunity to produce circuit implementations that are fully optimized for performance given the presence of process variations.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
Includes bibliographical references (p. 97-98).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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