dRMT: Disaggregated Programmable Switching
Name
drmt-sigcomm17.pdf
Description
Accepted version
Size
3.13 MB
Format
Adobe PDF
Checksum (MD5)
7bbc269c14e8682673869894a6bb44e9
Author(s)
Chole, Sharad
Fingerhut, Andy
Ma, Sha
Sivaraman, Anirudh
Vargaftik, Shay
Berger, Alon
Mendelson, Gal
Alizadeh, Mohammad
Chuang, Shang-Tse
Keslassy, Isaac
Date Issued
August 2017
Journal
SIGCOMM 2017 - Proceedings of the 2017 Conference of the ACM Special Interest Group on Data Communication
Publisher
Association for Computing Machinery (ACM)
Citation
Chole, Sharad, Fingerhut, Andy, Ma, Sha, Sivaraman, Anirudh, Vargaftik, Shay et al. 2017. "dRMT: Disaggregated Programmable Switching." SIGCOMM 2017 - Proceedings of the 2017 Conference of the ACM Special Interest Group on Data Communication.
Version
Author's final manuscript
Abstract
© 2017 ACM. We present dRMT (disaggregated Reconfigurable Match-Action Table), a new architecture for programmable switches. dRMT overcomes two important restrictions of RMT, the predominant pipelinebased architecture for programmable switches: (1) table memory is local to an RMT pipeline stage, implying that memory not used by one stage cannot be reclaimed by another, and (2) RMT is hardwired to always sequentially execute matches followed by actions as packets traverse pipeline stages. We show that these restrictions make it difficult to execute programs efficiently on RMT. dRMT resolves both issues by disaggregating the memory and compute resources of a programmable switch. Specifically, dRMT moves table memories out of pipeline stages and into a centralized pool that is accessible through a crossbar. In addition, dRMT replaces RMT's pipeline stages with a cluster of processors that can execute match and action operations in any order. We show how to schedule a P4 program on dRMT at compile time to guarantee deterministic throughput and latency. We also present a hardware design for dRMT and analyze its feasibility and chip area. Our results show that dRMT can run programs at line rate with fewer processors compared to RMT, and avoids performance cliffs when there are not enough processors to run a program at line rate. dRMT's hardware design incurs a modest increase in chip area relative to RMT, mainly due to the crossbar.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1145/3098822.3098823
