System-Technology Co-Optimization of Scaled Electronics
Based on Two-Dimensional Materials
Name
zhu-jdzhu-phd-eecs-2025-thesis.pdf
Description
Thesis PDF
Size
9.5 MB
Format
Adobe PDF
Checksum (MD5)
4c3cf42018c165f6a492d21b0c6e720d
Author(s)
Zhu, Jiadi
Advisor(s)
Palacios, Tomás
Date Issued
February 2025
Publisher
Massachusetts Institute of Technology
Abstract
Over the past 60 years, the semiconductor industry has focused on developing highly scaled electronic devices and high-density integrated circuits. However, bottlenecks have arisen recently as transistor dimensions approach the physical limits, and integration density is constrained. This thesis addresses these issues with two-dimensional (2D) materials, which includes inventing a low-temperature (< 300 °C) metal-organic chemical vapor deposition (MOCVD) method for 2D materials on 8-inch wafers, investigating extreme device scaling and multi-channel transistors. Design-Technology Co-Optimization (DTCO) and SystemTechnology Co-Optimization (STCO) are employed to rapidly model, evaluate and optimize device and circuit performance. Moreover, heterogeneous integration and monolithic 3D integration techniques are investigated, addressing challenges in integrating 2D materials with silicon complementary-metal-oxide-semiconductor (CMOS) circuits and flexible substrates. This research aims to advance high-density, high-performance electronics with low-power consumption for next-generation integrated systems.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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