A pipelined analog-to-digital converter with low-gain, low-bandwidth op-amps
Name
1005701141-MIT.pdf
Description
Full printable version
Size
7.58 MB
Format
Adobe PDF
Checksum (MD5)
2dd37a71023030d740485893185fbacf
Author(s)
Jeong, Taehoon
Advisor(s)
Anantha P. Chandrakasan and Hae-Seung Lee.
Date Issued
2017
Publisher
Massachusetts Institute of Technology
Abstract
Designing a high-gain, high-bandwidth op-amp for pipelined ADCs in fine-line CMOS technology has become increasingly challenging. In order to address this issue, this thesis presents the shadow-ADC-assisted digital calibration technique. The proposed technique relaxes op-amp performance requirements by removing op-amp-induced charge-transfer errors in the digital domain. A proof-of-concept pipelined ADC has been designed in 28nm FDSOI CMOS technology and is currently being fabricated.
Description
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 65-68).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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