Amplifier and data converter techniques for low power sensor interfaces
Name
973334133-MIT.pdf
Description
Full printable version
Size
14.98 MB
Format
Adobe PDF
Checksum (MD5)
0deb7a5fb8b6b287cc452ede7ae36386
Author(s)
Yaul, Frank M
Advisor(s)
Anantha P. Chandrakasan.
Date Issued
2016
Publisher
Massachusetts Institute of Technology
Abstract
Sensor interfaces circuits are integral components of wireless sensor nodes, and improvements to their energy-efficiency help enable long-term medical and industrial monitoring applications. This thesis explores both analog and algorithmic energy-saving techniques in the sensor interface signal chain. First, a data-dependent successive-approximation algorithm is developed and is demonstrated in a low-power analog-to-digital converter (ADC) implementation. When averaged over many samples, the energy per conversion and number of bitcycles per conversion used by this algorithm both scale logarithmically with the activity of the input signal, with each N-bit conversion using between 2 and 2N+1 bitcycles, compared to N for conventional binary SA. This algorithm reduces ADC power consumption when sampling signals with low mean activity, and its effectiveness is demonstrated on an electrocardiogram signal. With a 0.6V supply, the 10-bit ADC test chip has a maximum sample rate of 16 kHz and an effective number of bits (ENOB) of 9.73b. The ADC's Walden Figure of Merit (FoM) ranges from 3.5 to 20 fJ/conversion-step depending on the input signal activity. Second, an ultra-low supply voltage amplifier stage is developed and used to create an energy-efficient low-noise instrumentation amplifier (LNIA). This chopper LNIA uses a 0.2V-supply inverter-based input stage followed by a 0.8V-supply folded-cascode common-source stage. The high input-stage current needed to reduce the input-referred noise is drawn from the 0.2V supply, significantly reducing power consumption. The 0.8V stage provides high gain and signal swing, improving linearity. Biasing and common-mode rejection techniques for the 0.2V-stage are also presented. The analog front-end (AFE) test chip incorporating the chopper LNIA achieves a power-efficiency figure (PEF) of 1.6 with an input noise of 0.94 [mu]VRMS, integrated from 0.5 to 670 Hz. Human biopotential signals are measured using the AFE.
Description
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 151-157).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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