A 0.6V 2.9µW mixed-signal front-end for ECG monitoring
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Author(s)
Yip, Marcus
Bohorquez, Jose L.
Chandrakasan, Anantha P.
Date Issued
June 2012
Journal
Proceedings of the 2012 Symposium on VLSI Circuits (VLSIC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Yip, Marcus, Jose L. Bohorquez, and Anantha P. Chandrakasan. “A 0.6V 2.9µW Mixed-Signal Front-End for ECG Monitoring.” 2012 Symposium on VLSI Circuits (VLSIC) (June 2012).
Version
Author's final manuscript
Abstract
This paper presents a mixed-signal ECG front-end that uses aggressive voltage scaling to maximize power-efficiency and facilitate integration with low-voltage DSPs. 50/60Hz interference is canceled using mixed-signal feedback, enabling ultra-low-voltage operation by reducing dynamic range requirements. Analog circuits are optimized for ultra-low-voltage, and a SAR ADC with a dual-DAC architecture eliminates the need for a power-hungry ADC buffer. Oversampling and ΔΣ-modulation leveraging near-V[subscript T] digital processing are used to achieve ultra-low-power operation without sacrificing noise performance and dynamic range. The fully-integrated front-end is implemented in a 0.18μm CMOS process and consumes 2.9μW from 0.6V.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1109/VLSIC.2012.6243792
