Wire delay models for global placement of ASICs
Name
51588096-MIT.pdf
Description
Full printable version
Size
463.65 KB
Format
Adobe PDF
Checksum (MD5)
7a44897a3039138f98ec32019edc98ed
Author(s)
Paskalev, Krassimir (Krassimir Ivanov), 1978-
Advisor(s)
Michael Fu and Jacob K. White.
Alternative Title
Wire delay models for global placement of Application-Specific Integrated Circuits
Date Issued
2002
Publisher
Massachusetts Institute of Technology
Abstract
A new model for the propagation delay between two logic gates for timing-driven global placement is proposed. The model is a function of the number of pins on the net, the half perimeter of the bounding box enclosing the net, and the half perimeter of the bounding box enclosing the driving pin and the sink pin. On a training set of two designs and testing set of another two, the proposed model is 31% more accurate than the current state-of-the-art model and has comparable computational complexity.
Description
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
Includes bibliographical references (leaves 28-29).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
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