Author restrospective AEGIS: architecture for tamper-evident and tamper-resistant processing
Name
aegis-retro.pdf
Description
Accepted version
Size
201.45 KB
Format
Unknown
Checksum (MD5)
7b44c69c24d9afba2ec3727e42540d82
Author(s)
Suh, G. Edward
Fletcher, Christopher
Clarke, Dwaine
Gassend, Blaise
van Dijk, Marten
Devadas, Srinivas
Date Issued
2014
Publisher
Association for Computing Machinery (ACM)
Citation
Suh, G. Edward, Fletcher, Christopher, Clarke, Dwaine, Gassend, Blaise, van Dijk, Marten et al. 2014. "Author restrospective AEGIS: architecture for tamper-evident and tamper-resistant processing."
Version
Author's final manuscript
Abstract
AEGIS is a single-chip secure processor that can be used to protect the integrity and confidentiality of an application program from both physical and software attacks. We briefly describe the history behind this architecture and its key features, discuss main observations and lessons from the project, and list limitations of AEGIS and how recent research addresses them.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1145/2591635.2591665
