Bias-Stress Effect in Pentacene Organic Thin-Film Transistors
Name
Ryu-2010-Bias-Stress Effect in Pentacene Organic Thin-Film Transistors.pdf
Size
400.61 KB
Format
Adobe PDF
Checksum (MD5)
3c743b7c7ebf0ed027df6297a1bc628f
Author(s)
Ryu, Kevin K.
Nausieda, Ivan A.
He, David Da
Akinwande, Akintunde Ibitayo
Bulovic, Vladimir
Sodini, Charles G.
Date Issued
April 2010
Journal
IEEE Transactions on Electron Devices
Publisher
Institute of Electrical and Electronics Engineers
Citation
Ryu, K.K. et al. “Bias-Stress Effect in Pentacene Organic Thin-Film Transistors.” Electron Devices, IEEE Transactions On 57.5 (2010) : 1003-1008. ©2010 IEEE.
Version
Final published version
Abstract
The effects of bias stress in integrated pentacene organic transistors are studied and modeled for different stress conditions. It is found that the effects of bias stress can be expressed in terms of the shift in applied gate voltage [DELTA]V for a given current. An empirical equation describing [DELTA]V in terms of different gate and drain bias stress measurements and stress times is presented and verified. In the measured devices, [DELTA]V saturates at 14 V, independent of the gate bias-stress condition. A model based on carrier trapping rate equation that accounts for this [DELTA]V saturation is developed. The model suggests that the [DELTA]V saturation is due to the small density of traps compared to the channel carrier density.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Microsystems Technology Laboratories
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/ted.2010.2044282
