Synchronization on nulticore architectures
Name
880382523-MIT.pdf
Description
Full printable version
Size
5.18 MB
Format
Adobe PDF
Checksum (MD5)
1e7b017cd86c8199aea254971f564ed7
Author(s)
Harding, Rachael, S.M. Massachusetts Institute of Technology
Advisor(s)
Srinivas Devadas.
Date Issued
2014
Publisher
Massachusetts Institute of Technology
Abstract
The rise of multicore computing has made synchronization necessary to overcome the challenge of sharing data between multiple threads. Locks are critical synchronization primitives for maintaining data integrity and preventing race conditions in multithreaded applications. This thesis explores the lock design space. We propose a hardware lock implementation, called the lock arbiter, which reduces lock latency while minimizing hardware overheads and maintaining high levels of fairness between threads. We evaluate our mechanism against state-of-the-art software lock algorithms and find that our mechanism has comparable performance and fairness.
Description
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 53-55).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
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