Conv-RAM: An Energy-efficient SRAM with Embedded Convolution Computation for Low-power CNN based Machine Learning Applications
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ISSCC2018_manuscript.pdf
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1.28 MB
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Author(s)
Biswas, Avishek
Chandrakasan, Anantha P
Date Issued
March 2018
Journal
2018 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Biswas, Avishek and Anantha P. Chandrakasan. "Conv-RAM: An Energy-efficient SRAM with Embedded Convolution Computation for Low-power CNN based Machine Learning Applications." 2018 IEEE International Solid-State Circuits Conference (ISSCC), February 2018, San Francisco, California, USA, Institute of Electrical and Electronics Engineers (IEEE) March 2018 © 2018 IEEE
Version
Author's final manuscript
Abstract
Convolutional neural networks (CNN) provide state-of-the-art results in a wide variety of machine learning (ML) applications, ranging from image classification to speech recognition. However, they are very computationally intensive and require huge amounts of storage. Recent work strived towards reducing the size of the CNNs: [1] proposes a binary-weight-network (BWN), where the filter weights (w i 's) are ±1 (with a common scaling factor per filter: α). This leads to a significant reduction in the amount of storage required for the W i 's, making it possible to store them entirely on-chip. However, in a conventional all-digital implementation [2, 3], reading the wj i s and the partial sums from the embedded SRAMs require a lot of data movement per computation, which is energy-hungry. To reduce data-movement, and associated energy, we present an SRAM-embedded convolution architecture (Fig. 31.1.1), which does not require reading the w i 's explicitly from the memory. Prior work on embedded ML classifiers have focused on 1b outputs [4] or a small number of output classes [5], both of which are not sufficient for CNNs. This work uses 7b inputs/outputs, which is sufficient to maintain good accuracy for most of the popular CNNs [1]. The convolution operation is implemented as voltage averaging (Fig. 31.1.1), since the wj's are binary, while the averaging factor (1/N) implements the weight-coefficient α (with a new scaling factor, M, implemented off-chip).
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1109/ISSCC.2018.8310397
