A Multi-process Design of Paging System
Name
MIT-LCS-TR-171.pdf
Size
5.09 MB
Format
Adobe PDF
Checksum (MD5)
0581768cae08d44f9bf7f227872be410
Author(s)
Huber, Andrew R.
Advisor(s)
Clark, David D.
Date Issued
December 1976
Series/Report no.
MIT-LCS-TR-171
Abstract
This thesis presents a design for a paging system that may be used to implement a virtual memory on a large scale, demand paged computer utility. A model for such a computer system with a multi-level, hierarchical memory system is presented. The functional requirements of a paging system for such a model are discussed, with emphasis on the parallelism inherent in the algorithms used to implement the memory management functions.
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