A PCI Express to PCIX Bridge optimized for performance and area
Name
56823037-MIT.pdf
Description
Full printable version
Size
1.54 MB
Format
Adobe PDF
Checksum (MD5)
547e4389c2d2f05791bbe7aad631ff9a
Author(s)
Chong, Margaret J. (Margaret Jane), 1981-
Advisor(s)
Peter J. Jenkins , Jeffrey LaFramboise and Christopher J. Terman.
Date Issued
2004
Publisher
Massachusetts Institute of Technology
Abstract
This thesis project involves the architecture, implementation, and verification of a high bandwidth, low cost ASIC digital logic core that is compliant with the PCI Express to PCIX Bridge Specification. The core supports PCI Express and PCIX transactions, x16 PCI Express link widths, 32 and 64-bit PCIX link widths, all PCI Express and PCIX packet sizes, transaction ordering and queuing, relaxed ordering, flow control, and buffer management. Performance and area are optimized at the architectural and logic levels. The core is approximately 27K gate count, runs at a maximum of 250 MHz, and is synthesized to a current standard technology. This thesis explores PCI Express, PCIX, and PCI technologies, architectural design, development of Verilog and Vera models, thorough module-level verification, the development of a PCI Express/PCIX system verification environment, synthesis, static timing analysis, and performance and area evaluations. The work has been completed in IBM Microelectronics in Burlington, Vermont as part of the MIT VI-A Program.
Description
Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2004.
Includes bibliographical references (leaf 89).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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