A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications
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Author(s)
Tikekar, Mehul
Huang, Chao-Tsung
Sze, Vivienne
Chandrakasan, Anantha P.
Juvekar, Chiraag Shashikant
Date Issued
October 2013
Journal
IEEE Journal of Solid-State Circuits
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Tikekar, Mehul, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, and Anantha P. Chandrakasan. “A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications.” IEEE Journal of Solid-State Circuits 49, no. 1 (n.d.): 61–72.
Version
Author's final manuscript
Abstract
High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than [H.264 over AVC] to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes-a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 mm[superscript 2] in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 [nJ over pixel] of normalized system power.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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DOI of Published Version
https://doi.org/10.1109/jssc.2013.2284362
