Silicon-photonic clos networks for global on-chip communication
Name
Joshi-2009-Silicon-photonic clos networks for global on-chip communication.pdf
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468.52 KB
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Author(s)
Stojanovic, Vladimir Marko
Asanovic, Krste
Shamim, Imran
Beamer, Scott
Kwon, Yong-Jin
Batten, Christopher
Joshi, Ajay J.
Date Issued
June 2009
Journal
Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCS 2009)
Publisher
Institute of Electrical and Electronics Engineers
Citation
Joshi, A. et al. “Silicon-photonic clos networks for global on-chip communication.” Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on. 2009. 124-133. © 2009 IEEE
Version
Final published version
Abstract
Future many core processors will require energy-efficient, high-throughput on-chip networks. Silicon-photonics is a promising new interconnect technology which offers lower power, higher bandwidth density, and shorter latencies than electrical interconnects. In this paper we explore using photonics to implement low-diameter non-blocking crossbar and Clos networks. We use analytical modeling to show that a 64-tile photonic Clos network consumes significantly less optical power, thermal tuning power, and area compared to global photonic crossbars over a range of photonic device parameters. Compared to various electrical on-chip networks, our simulation results indicate that a photonic Clos network can provide more uniform latency and throughput across a range of traffic patterns while consuming less power. These properties will help simplify parallel programming by allowing the programmer to ignore network topology during optimization.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
http://dx.doi.org/10.1109/NOCS.2009.5071460
