A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC
Name
Brooks-2009-A 12b, 50 MS_s, Full.pdf
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1.54 MB
Format
Adobe PDF
Checksum (MD5)
a36807e0457dbf78114dbf0f02696827
Author(s)
Brooks, Lane
Lee, Hae-Seung
Date Issued
December 2009
Journal
IEEE Journal of Solid-State Circuits
Publisher
Institute of Electrical and Electronics Engineers
Citation
Brooks, L., and Hae-Seung Lee. “A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC.” Solid-State Circuits, IEEE Journal of 44.12 (2009): 3329-3343. © 2009 IEEE
Version
Final published version
Abstract
Zero-crossing based switch capacitor circuits have been introduced as alternatives to op-amp based circuits for eased design considerations and improved power efficiency. This work further improves the resolution, power efficiency, and robustness of previous zero-crossing based circuits (ZCBCs) and features a 90 nm CMOS, offset compensated, fully differential, zero-crossing based, 12b, 50 MS/s, pipelined ADC requiring no CMFB. The power consumption is 4.5 mW. The FOM is 88 fJ/step. Fully differential signaling is used to improve power supply rejection and power efficiency. A power efficient chopping offset compensation technique is presented. Reference voltage switching is improved to avoid gate boosted switches. Redundancy is used to reduce output range requirements for increased signal range. Two regenerative latch architectures used for bit decision comparison are analyzed and measured for offset, noise, and speed.
Subjects
zero-crossing based circuits
scaled CMOS
offset compensation
comparator-based switched-capacitor circuits
chopping
chopper stabilization
ZCBC
CHS
CBSC
ADC
A/D
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
http://dx.doi.org/10.1109/JSSC.2009.2032639
