ATAC: A 1000-Core Cache-Coherent Processor with On-Chip Optical Network
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Agarwal_ATAC a.pdf
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Author(s)
Kurian, George
Miller, Jason E.
Psota, James R.
Eastep, Jonathan Michael
Liu, Jifeng
Michel, Jurgen
Kimerling, Lionel C.
Agarwal, Anant
Date Issued
September 2010
Journal
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques
Publisher
Association for Computing Machinery
Citation
Kurian, George et al. “ATAC.” ACM Press, 2010. 477. Web. 9 Dec. 2011. © 2010 Association for Computing Machinery
Version
Author's final manuscript
Abstract
Based on current trends, multicore processors will have 1000 cores or more within the next decade. However, their promise of increased performance will only be realized if their inherent scaling and programming challenges are overcome. Fortunately, recent advances in nanophotonic device manufacturing are making CMOS-integrated optics a reality-interconnect technology which can provide significantly more bandwidth at lower power than conventional electrical signaling. Optical interconnect has the potential to enable massive scaling and preserve familiar programming models in future multicore chips.
This paper presents ATAC, a new multicore architecture with integrated optics, and ACKwise, a novel cache coherence protocol designed to leverage ATAC's strengths. ATAC uses nanophotonic technology to implement a fast, efficient global broadcast network which helps address a number of the challenges that future multicores will face. ACKwise is a new directory-based cache coherence protocol that uses this broadcast mechanism to provide high performance and scalability. Based on 64-core and 1024-core simulations with Splash2, Parsec, and synthetic benchmarks, we show that ATAC with ACKwise out-performs a chip with conventional interconnect and cache coherence protocols. On 1024-core evaluations, ACKwise protocol on ATAC outperforms the best conventional cache coherence protocol on an electrical mesh network by 2.5x with Splash2 benchmarks and by 61% with synthetic benchmarks.
MIT Department
Massachusetts Institute of Technology. Materials Processing Center
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Department of Materials Science and Engineering
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Creative Commons Attribution-Noncommercial-Share Alike 3.0
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DOI of Published Version
https://doi.org/10.1145/1854273.1854332
