Strategies for manufacturing low volume semiconductor products in a high volume manufacturing environment
Name
50650732-MIT.pdf
Description
Full printable version
Size
8 MB
Format
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Checksum (MD5)
c2c7559ea3c8dd0ada0bdf382708338f
Author(s)
Scholtz, Robert L. (Robert Louis), 1972-
Advisor(s)
Jesús A. del Alamo and Stephen C. Graves.
Date Issued
2002
Publisher
Massachusetts Institute of Technology
Abstract
The rapid growth of the digital communications market has prompted several large semiconductor manufacturers, including Intel Corporation, to begin the design and manufacture of communication ICs. The communications ICs are currently produced in much lower volumes than products such as microprocessors and memory. These low-volume products have been reported to cause operational problems, such as excessive cost, slow throughput time, and low yield when manufactured in semiconductor fabs designed for high volume manufacturing. This thesis examines the operational problems caused by the manufacture of low-volume semiconductor products and explores potential improvements. A financial model was developed to compare the cost of manufacturing low-volume products using several different strategies in existing high-volume fabs. The model results demonstrated that mask set cost, a fixed cost, becomes a very large component of total production cost as the product volume is reduced. Further, this model identified multi-product wafers, a scheme of fabricating several products on a single wafer, as a strategy with potential for savings up to approximately 75% of the manufacturing cost of low-volume products. A second financial model was developed to consider more detailed aspects of fabricating products on multi-product wafers. This model considered the sensitivity of the potential cost savings to changes in demand and changes to the design of multi-product wafers. This model also demonstrated that significant savings are possible with the multi-product wafer strategy, especially if the products are carefully matched (by die size and demand) with other products on the multi-product wafer. Finally, a brief organizational study was conducted to analyze the implementation of a multi-product wafer manufacturing process for the production of low-volume CMOS ICs at Intel Corporation.
Description
Thesis (M.B.A.)--Massachusetts Institute of Technology, Sloan School of Management; and, (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering; in conjunction with the Leaders for Manufacturing Program at MIT, 2002.
Includes bibliographical references (p. 82-83).
Subjects
Sloan School of Management.
Mechanical Engineering.
Leaders for Manufacturing Program.
MIT Department
Leaders for Manufacturing Program at MIT
Massachusetts Institute of Technology. Department of Mechanical Engineering
Sloan School of Management
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