Spinal codes
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Balakrishnan_Spinal codes.pdf
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Author(s) • • • •
Perry, Jonathan
Iannucci, Peter A.
Fleming, Kermin Elliott
Balakrishnan, Hari
Shah, Devavrat
Date Issued
October 2012
Journal
ACM SIGCOMM Computer Communication Review
Publisher
Association for Computing Machinery
Citation
Perry, Jonathan, Peter A. Iannucci, Kermin E. Fleming, Hari Balakrishnan, and Devavrat Shah. “Spinal Codes.” ACM SIGCOMM Computer Communication Review 42, no. 4 (October 2012): 49-60.
Version
Author's final manuscript
Abstract
Spinal codes are a new class of rateless codes that enable wireless networks to cope with time-varying channel conditions in a natural way, without requiring any explicit bit rate selection. The key idea in the code is the sequential application of a pseudo-random hash function to the message bits to produce a sequence of coded symbols for transmission. This encoding ensures that two input messages that differ in even one bit lead to very different coded sequences after the point at which they differ, providing good resilience to noise and bit errors. To decode spinal codes, this paper develops an approximate maximum-likelihood decoder, called the bubble decoder, which runs in time polynomial in the message size and achieves the Shannon capacity over both additive white Gaussian noise (AWGN) and binary symmetric channel (BSC) models. Experimental results obtained from a software implementation of a linear-time decoder show that spinal codes achieve higher throughput than fixed-rate LDPC codes, rateless Raptor codes, and the layered rateless coding approach of Strider, across a range of channel conditions and message sizes. An early hardware prototype that can decode at 10 Mbits/s in FPGA demonstrates that spinal codes are a practical construction.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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DOI of Published Version
https://doi.org/10.1145/2377677.2377684