Efficient pipelining of nested loops : unroll-and-squash
Name
51626122-MIT.pdf
Description
Full printable version
Size
205.99 KB
Format
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Checksum (MD5)
1e4e08d3a22f3f0fe466b279d39e9f8e
Author(s)
Petkov, Darin S. (Darin Stamenov), 1977-
Advisor(s)
Randolph E. Harr and Saman P. Amarasinghe.
Date Issued
2001
Publisher
Massachusetts Institute of Technology
Abstract
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology to map abstract designs into silicon. Many applications operating on large streaming data usually require a custom VLSI because of high performance or low power restrictions. Since the data processing is typically described by loop constructs in a high-level language, loops are the most critical portions of the hardware description and special techniques are developed to optimally synthesize them. In this thesis, we introduce a new method for mapping nested loops into hardware and pipelining them efficiently. The technique achieves fine-grain parallelism even on strong intra- and inter-iteration data-dependent inner loops and, by economically sharing resources, improves performance at the expense of a small amount of additional area. We implemented the transformation within the Nimble Compiler environment and evaluated its performance on several signal-processing benchmarks. The method achieves up to 2x increase in the area efficiency compared to the best known optimization techniques.
Description
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
Includes bibliographical references (leaves 49-50).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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