Integration of silicon photonics into electronic processes
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Ram_Integration of.pdf
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Author(s)
Orcutt, Jason Scott
Ram, Rajeev J.
Stojanovic, Vladimir
Date Issued
March 2013
Journal
Proceedings of SPIE--the International Society for Optical Engineering ; volume 8629
Publisher
Society of Photo-Optical Instrumentation Engineers (SPIE)
Citation
Orcutt, Jason S., Rajeev J. Ram, and Vladimir Stojanović. “Integration of Silicon Photonics into Electronic Processes.” Edited by Joel Kubby and Graham T. Reed. Silicon Photonics VIII (March 14, 2013), San Francisco, California, United States. (Proceedings of SPIE ; volume 8629). SPIE © 2013.
Version
Final published version
Abstract
Front-end monolithic integration has enabled photonic devices to be fabricated in bulk and thin-SOI CMOS as well as DRAM electronics processes. Utilizing the CMOS generic process model, integration was accomplished on multi-project wafers that were shared by standard electronic customers without requiring in-foundry process changes. Simple die or wafer-level post-processing has enabled low-loss waveguides by the removal of the substrate within photonic regions. The custom-process model of the DRAM industry instead enabled optimization of the photonic device fabrication process and the potential elimination of post-processing requirements. Integrated singlecrystalline silicon waveguide loss of ~3 dB/cm has been achieved within a 45nm thin-SOI CMOS process that is currently used to manufacture microprocessors [1]. A fully monolithic photonic transmitter including a pseudo-random bit sequence (PRBS) generating digital backend was also demonstrated within this process [1]. The constraints of zero-change integration have limited achieved polysilicon waveguide loss to ~50 dB/cm with commercially available bulk CMOS processes [2]. Custom polysilicon deposition and processing conditions available for DRAM integration have also led to the demonstration of ~6 dB/cm loss waveguides suitable for integration within electronics processes utilizing bulk silicon starting substrates [3]. An overview of required process features, device design guidelines and integration methodology tradeoffs will be presented. Relevant device metrics of area and energy efficiency as well as achievable photonic device performance will be presented within the context of monolithic front-end integration within state-ofthe- art electronics processes. Applications of this research towards the implementation of a computer system utilizing photonic interconnect for core-to-memory communication will also be discussed.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1117/12.2004811
