Generating efficient layouts from optimized MOS circuit schematics

Name

RLE-TR-535-19401467.pdf

Size

9.84 MB

Format

Adobe PDF

Checksum (MD5)

fd9ea37e554a77a210f3ab44f732bb77

Date Issued

1988

Publisher

Research Laboratory of Electronics, Massachusetts Institute of Technology

Series/Report no.

Technical report (Massachusetts Institute of Technology. Research Laboratory of Electronics) ; 535.

Description

Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.

Includes bibliographical references.

MIT Department

Massachusetts Institute of Technology. Research Laboratory of Electronics

Persistent DSpace Link