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Generating efficient layouts from optimized MOS circuit schematics

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RLE-TR-535-19401467.pdf

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Date Issued
1988
Publisher
Research Laboratory of Electronics, Massachusetts Institute of Technology
Series/Report no.
Technical report (Massachusetts Institute of Technology. Research Laboratory of Electronics) ; 535.
Description
Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.
Includes bibliographical references.
MIT Department
Massachusetts Institute of Technology. Research Laboratory of Electronics
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