Catalyst Self-Assembly for Scalable Patterning of Sub 10 nm Ultrahigh Aspect Ratio Nanopores in Silicon
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Grossman_Catalyst self-assembly.pdf
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Author(s)
Smith, Brendan Derek
Patil, Jatin J
Ferralis, Nicola
Grossman, Jeffrey C.
Date Issued
March 2016
Journal
ACS Applied Materials & Interfaces
Publisher
American Chemical Society (ACS)
Citation
Smith, Brendan D. et al. “Catalyst Self-Assembly for Scalable Patterning of Sub 10 nm Ultrahigh Aspect Ratio Nanopores in Silicon.” ACS Applied Materials & Interfaces 8, 12 (March 2016): 8043–8049 © 2016 American Chemical Society
Version
Author's final manuscript
Abstract
Nanoporous silicon (NPSi) has received significant attention for its potential to contribute to a large number of applications, but has not yet been extensively implemented because of the inability of current state-of-the-art nanofabrication techniques to achieve sufficiently small pore size, high aspect ratio, and process scalability. In this work we describe the fabrication of NPSi via a modified metal-assisted chemical etching (MACE) process in which silica-shell gold nanoparticle (SiO₂-AuNP) monolayers self-assemble from solution onto a silicon substrate. Exposure to the MACE etchant solution results in the rapid consumption of the SiO₂ spacer shell, leaving well-spaced arrays of bare AuNPs on the substrate surface. Particles then begin to catalyze the etching of nanopore arrays without interruption, resulting in the formation of highly anisotropic individual pores. The excellent directionality of pore formation is thought to be promoted by the homogeneous interparticle spacing of the gold core nanocatalysts, which allow for even hole injection and subsequent etching along preferred crystallographic orientations. Electron microscopy and image analysis confirm the ability of the developed technique to produce micrometer-scale arrays of sub 10 nm nanopores with narrow size distributions and aspect ratios of over 100:1. By introducing a scalable process for obtaining high aspect ratio pores in a novel size regime, this work opens the door to implementation of NPSi in numerous devices and applications. (Graph Presented).
MIT Department
Massachusetts Institute of Technology. Department of Materials Science and Engineering
Massachusetts Institute of Technology. Research Laboratory of Electronics
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DOI of Published Version
https://doi.org/10.1021/ACSAMI.6B01927
