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A Common Backend for Hardware Acceleration on FPGA
Name
frost_workshop.pdf
Description
Accepted version
Size
177.63 KB
Format
Adobe PDF
Checksum (MD5)
195fe18c8922bb2aec64bebce5eab5eb
Author(s)
Del Sozzo, Emanuele
Baghdadi, Riyadh
Amarasinghe, Saman
Santambrogio, Marco D.
Date Issued
November 2017
Publisher
IEEE
Citation
Del Sozzo, Emanuele, Baghdadi, Riyadh, Amarasinghe, Saman and Santambrogio, Marco D. 2017. "A Common Backend for Hardware Acceleration on FPGA."
Version
Author's final manuscript
Abstract
© 2017 IEEE. Field Programmable Gate Arrays (FPGAs) are configurable integrated circuits able to provide a good trade-off in terms of performance, power consumption, and flexibility with respect to other architectures, like CPUs, GPUs and ASICs. The main drawback in using FPGAs, however, is their steep learning curve. An emerging solution to this problem is to write algorithms in a Domain Specific Language (DSL) and to let the DSL compiler generate efficient code targeting FPGAs. This work proposes FROST, a unified backend that enables different DSL compilers to target FPGA architectures. Differently from other code generation frameworks targeting FPGA, FROST exploits a scheduling co-language that enables users to have full control over which optimizations to apply in order to generate efficient code (e.g. loop pipelining, array partitioning, vectorization). At first, FROST analyzes and manipulates the input Abstract Syntax Tree (AST) in order to apply FPGA-oriented transformations and optimizations, then generates a C/C++ implementation suitable for High-Level Synthesis (HLS) tools. Finally, the output of HLS phase is synthesized and implemented on the target FPGA using Xilinx SDAccel toolchain. The experimental results show a speedup up of 15 with respect to O3-optimized implementations of the same algorithms on CPU.
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
10.1109/iccd.2017.75
