Multitrack power factor correction architecture
Name
multitrackpfc_paper.pdf
Description
Accepted version
Size
4.59 MB
Format
Adobe PDF
Checksum (MD5)
2296a0c9ca5abfc67f52c561cc10aff1
Author(s)
Chen, Minjie
Perreault, David J.
Date Issued
March 2019
Journal
IEEE Transactions on Power Electronics
Publisher
IEEE
Citation
Chen, Minjie, Sombuddha Chakraborty and David J. Perreault. "Multitrack Power Factor Correction Architecture." IEEE Transactions on Power Electronics 34, no.3 (March 2019): pp. 2454-2466 © 2018 The Author(s)
Version
Author's final manuscript
Abstract
Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high power density and high efficiency as a new development of the Multitrack concept [1]. The proposed Multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching (ZVS) at high frequencies (HF, 1-3 MHz) across universal input voltage range (85Vac-265Vac) and wide power range. The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This Multitrack concept is compatible with a wide range of existing design techniques for PFC systems. A prototype 150W, universal ac input, 12VDC output, isolated Multitrack PFC system with a power density of 50W/inch3 and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the Multitrack PFC architecture.
MIT Department
Massachusetts Institute of Technology. Research Laboratory of Electronics
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/apec.2018.8341094
