Equivalence checking of retimed circuits
Name
62324849-MIT.pdf
Description
Full printable version
Size
531 KB
Format
Adobe PDF
Checksum (MD5)
4928ef52601e74f16f77f143f9655745
Author(s)
Netolická, Karolína
Advisor(s)
Philip Baraona and Arvind.
Date Issued
2005
Publisher
Massachusetts Institute of Technology
Abstract
This thesis addresses the problem of verifying the equivalence of two circuits, one or both of which have undergone register retiming as well as logic resynthesis. The aim of the thesis is to improve the ability of Formality, an equivalence checking tool written at Synopsys, to handle retimed circuits. At the beginning of this project Formality already had an implementation of peripheral retiming, an algorithm that can handle a large set of retimed circuits. In this thesis, I explain the performance, usability and special case coverage problems found in the original implementation. I review other retiming verification algorithms and conclude that none of them would perform satisfactorily in Formality. Finally, I explain the modifications made to peripheral retiming in order to solve some of the identified issues and propose partial solutions for the problems that have not been solved yet.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (p. 25).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Persistent DSpace Link
