A power reduction algorithm for combinatorial CMOS circuits using input disabling
Name
32906126-MIT.pdf
Description
Full printable version
Size
2.68 MB
Format
Adobe PDF
Checksum (MD5)
4c839b42098e71d9361a26cd42e0a3b6
Author(s)
Rinderknecht, William John
Advisor(s)
Srinivas Devadas.
Date Issued
1995
Publisher
Massachusetts Institute of Technology
Description
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
Includes bibliographical references (p. 61-62).
Subjects
Electrical Engineering and Computer Science
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
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