A comparative analysis of physical-layer rateless coding architectures
Name
890152009-MIT.pdf
Description
Full printable version
Size
9.61 MB
Format
Adobe PDF
Checksum (MD5)
d151d7e1a25d146cf3db63cdbb9e88a8
Author(s)
Romero, David Luis
Advisor(s)
Gregory W. Wornell and Adam R. Margetts.
Date Issued
2014
Publisher
Massachusetts Institute of Technology
Abstract
An analysis of rateless codes implemented at the physical layer is developed. Our model takes into account two aspects of practical communication system design that are abstracted away in many existing works on the subject. In particular, our model assumes that : (1) practical error detection methods are used to determine when to terminate decoding; and (2) performance and reliability as observed at the transport layer are the metrics of interest. Within the context of these assumptions, we then evaluate two recently proposed high-performing rateless codes. Using our analysis to guide an empirical study, the process of selecting the best rateless code for a given set of system constraints is illustrated.
Description
Thesis: S.M. in Electrical Engineering, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
21
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 113-114).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
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