High-speed modulation of resonant CMOS photonic modulators in deep-submicron CMOS
Name
900638523-MIT.pdf
Description
Full printable version
Size
22.23 MB
Format
Adobe PDF
Checksum (MD5)
f91efc9e6c79ee174eae0174840595f9
Author(s)
Moss, Benjamin (Benjamin Roy)
Advisor(s)
Vladimir Stojanović.
Date Issued
2014
Publisher
Massachusetts Institute of Technology
Abstract
Processor manufacturers have turned to parallelism to continue to improve processor performance, and the bandwidth demands of manycore systems are rising. Silicon photonics can lower the energy-per-bit of core-to-core and core-to-memory interconnects while simultaneously alleviating bandwidth bottlenecks. In this work, methods of controlling the amount of charge entering the diode structure of a photonic modulator are investigated to achieve high energy efficiency in a constrained monolithic process. Two digital modulator topologies are simulated, fabricated and tested. One circuit topology, intended to drive a carrier-injection-based ring modulator, uses a digital push-pull topology with preemphasis to reduce the energy-per-bit and to prevent the ring's optical passband from shifting to the next optical channel. The second circuit topology drives a depletion-mode modulator device for high energy efficiency and speed. High-level system modeling is addressed, as well as practical considerations such as packaging. This work marks the first monolithic transceiver in a zero-change CMOS process, and the most energy-efficient monolithically-integrated modulator in a sub-100 nm CMOS process.
Description
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 161-164).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
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