A Low-power Area-efficient Switching Scheme for Charge-sharing DACs in SAR ADCs
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Chandrakasan-a low-power.pdf
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Author(s)
Chen, Fred Fu-Chin
Chandrakasan, Anantha P.
Stojanovic, Vladimir Marko
Date Issued
September 2010
Journal
2010 IEEE Custom Integrated Circuits Conference (CICC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Chen, Fred, Anantha P. Chandrakasan, and Vladimir Stojanovic. “A Low-power Area-efficient Switching Scheme for Charge-sharing DACs in SAR ADCs.” 2010 IEEE Custom Integrated Circuits Conference (CICC), 2010. 1–4. © Copyright 2010 IEEE
Version
Final published version
Abstract
Analysis and experimental results for a new switching scheme and topology for charge sharing DACs used in successive approximation register (SAR) ADCs is presented. The characteristics of the SAR algorithm are exploited to develop a switching scheme that reduces the number of required unit capacitors by nearly an order of magnitude over conventional charge sharing DACs without the aid of any additional reference voltages. The proposed topology also enables a rail-to-rail voltage swing at the DAC output enabling a differential voltage input at the ADC of up to twice the supply voltage. An 8-bit SAR ADC using the proposed DAC is implemented in a 90nm CMOS process and consumes 700 nW at 0.7 V and 100 kS/s while occupying 0.0135 mm[superscript 2].
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/CICC.2010.5617461
