Discrete-time, cyclostationary phase-locked loop model for jitter analysis
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Vamvakos-2009-Discrete-time, cyclostationary phase-locked loop model for jitter analysis.pdf
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654.79 KB
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Checksum (MD5)
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Author(s)
Vamvakos, Socrates D.
Stojanovic, Vladimir Marko
Nikolic, Borivoje
Date Issued
October 2009
Journal
Proceedings of the Custom Integrated Circuits Conference, 2009
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Vamvakos, Socrates D., Vladimir Stojanovic, and Borivoje Nikolic. “Discrete-time, Cyclostationary Phase-locked Loop Model for Jitter Analysis.” IEEE, 2009. 637–640. © 2012 IEEE
Version
Final published version
Abstract
Timing jitter is one of the most significant phase-locked loop characteristics, with high impact on performance in a range of applications. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, cyclostationary PLL model for jitter analysis is proposed, which accounts for the cyclostationary nature of noise injected into the loop at various PLL components. The model also predicts the aliasing of jitter due to the downsampling and upsampling of frequencies around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a 3[superscript rd]-order PLL.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/CICC.2009.5280745
