Graph-based representations and coupled verification of VLSI schematics and layouts

Name

RLE-TR-547-20860899.pdf

Size

11.67 MB

Format

Adobe PDF

Checksum (MD5)

cb79e1ba9420c4273fb25b116c6f7f31

Date Issued

1989

Publisher

Research Laboratory of Electronics, Massachusetts Institute of Technology

Series/Report no.

Technical report (Massachusetts Institute of Technology. Research Laboratory of Electronics) ; 547.

Description

Includes bibliographical references (p. 199-202).

MIT Department

Massachusetts Institute of Technology. Research Laboratory of Electronics

Persistent DSpace Link