A comparator-based switched-capacitor pipelined analog-to-digital converter
Name
191822802-MIT.pdf
Description
Full printable version
Size
1.26 MB
Format
Adobe PDF
Checksum (MD5)
4b7ec4c655210aa7fda5efc182204d98
Author(s)
Fiorenza, John Kenneth, 1977-
Advisor(s)
Hae-Seung Lee and Charles G. Sodini.
Alternative Title
CBSC pipelined analog-to-digital converter
Date Issued
2007
Publisher
Massachusetts Institute of Technology
Abstract
A new comparator-based switched-capacitor(CBSC) technique is proposed that eliminates the need for high gain op-amps in switched-capacitor circuits. The CBSC technique replaces the op-amp in switched-capacitor circuits with a comparator and a current source. Compared to op-amps, comparators suffer less from the negative effects of scaled CMOS. The technique is applicable to a broad class of sampled-data circuits including analog-to-digital converters, digital-to-analog converters, sample-and-holds, integrators and filters. As a proof of concept the technique is demonstrated in the design of a pipelined analog-to-digital converter. The prototype CBSC 1.5 b/stage pipelined ADC implemented in a 0.18 [mu]m CMOS process operates at 7.9MHz, achieves 8.6 effective bits of accuracy, and consumes 2.5mW of power. Sources of offset and nonlinearity are identified and analyzed. The analysis reveals the potential of the CBSC technique for lower power dissipation and provides design guidelines for energy efficient comparator-based switched-capacitor circuit design.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (leaves 112-115).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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