Evaluating the Feasibility of Transaction Scheduling via Hardware Accelerators
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chomphoochan-tcpc-meng-eecs-2025-thesis.pdf
Description
Thesis PDF
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956.66 KB
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Author(s)
Chomphoochan, Thanadol
Advisor(s)
Chlipala, Adam
Date Issued
May 2025
Publisher
Massachusetts Institute of Technology
Abstract
As single-thread performance plateaus, modern systems increasingly rely on parallelism to scale throughput. Yet, efciently managing concurrency—particularly in transactional systems—remains a major bottleneck. This thesis explores the feasibility of accelerating transaction scheduling via hardware, leveraging FPGAs to ofoad scheduling logic from the CPU. We revisit Puppetmaster, a hardware transaction scheduler, and present a redesigned architecture emphasizing deployability, modularity, and evaluation. We implement both an optimized software baseline and a Bluespec-based hardware design, evaluating their performance across synthetic YCSB-style workloads with varying contention levels. Our hardware prototype demonstrates competitive throughput, achieving over 90% of peak throughput even under high-contention workloads. These results validate the potential of transaction scheduling as a target for hardware acceleration and highlight promising directions for future hybrid hardware-software concurrency-control systems.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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