Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators
Name
MIT-LCS-TM-491.pdf
Size
139.26 KB
Format
Adobe PDF
Checksum (MD5)
9c44f35f1cee11d28ec73ea1049e52c8
Author(s)
Babb, Jonathan
Tessier, Russell
Agarwal, Anant
Date Issued
November 1992
Series/Report no.
MIT-LCS-TM-491
Abstract
Existing FPGA-based logic emulators suffer from limited inter-chip communication bandwidth, resulting in low gate utilization (10 20 percent). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals must cross more chip boundaries. Current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). These logical wires are not active simultaneously are only switched at emulation clock speeds.
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