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  5. Prototyping a scalable massively-parallel supercomputer architecture with FPGAs

Prototyping a scalable massively-parallel supercomputer architecture with FPGAs

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Author(s)
Phillips, Michael P. (Michael Patrick), 1977-
Advisor(s)
Thomas F. Knight, Jr.
Alternative Title
Prototyping a scalable massively-parallel supercomputer architecture with field programmable gate arrays
Date Issued
2001
Publisher
Massachusetts Institute of Technology
Description
Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
Includes bibliographical references (p. 97-101).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Persistent DSpace Link
http://hdl.handle.net/1721.1/86697
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