Building blocks of a 250MHz bandwidth, 10-bit continuous-time delta-sigma analog to digital converter
Name
894502748-MIT.pdf
Description
Full printable version
Size
8.79 MB
Format
Adobe PDF
Checksum (MD5)
dab1722915ec59b48c999e590eba8c85
Author(s)
Zhu, Xianzhen
Advisor(s)
Charles G. Sodini and Benjamin Walker.
Alternative Title
Design blocks of a continuous-time delta-sigma ADC in a BiCMOS technology
Date Issued
2014
Publisher
Massachusetts Institute of Technology
Abstract
This thesis examines the design of a continuous time Delta-Sigma Analog to Digital Converter with the target performance to be 10-bit, 250MHz bandwidth with 200mW power dissipation.The design process involves choosing a top-level architecture and designing transistor-level blocks. The architecture is selected to be second-order, 3-bit with a 32 oversampling rate based on the ideal model simulation in MATLAB. The transistor-level circuits are designed in a BiCMOS technology. The SQNR result is 63.3dB and the power is 140mW.
Description
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 93-94).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
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