A Low-Latency, Low-Area Hardware Oblivious RAM Controller
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Devadas_A low-latency.pdf
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Author(s)
Fletcher, Christopher Wardlaw
Ren, Ling
Kwon, Young Hyun
van Dijk, Marten
Stefanov, Emil
Serpanos, Dimitrios
Devadas, Srinivas
Date Issued
May 2015
Journal
Proceedings of the IEEE 23rd International Symposium on Field-Programmable Custom Computing Machines
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Fletcher, Christopher W., Ling Ren, Albert Kwon, Marten van Dijk, Emil Stefanov, Dimitrios Serpanos, and Srinivas Devadas. "A Low-Latency, Low-Area Hardware Oblivious RAM Controller." IEEE 23rd International Symposium on Field-Programmable Custom Computing Machines, May 3-5, 2015.
Version
Author's final manuscript
Abstract
We build and evaluate Tiny ORAM, an Oblivious RAM prototype on FPGA. Oblivious RAM is a cryptographic primitive that completely obfuscates an application’s data, access pattern, and read/write behavior to/from external memory (such as DRAM or disk). Tiny ORAM makes two main contributions. First, by removing an algorithmic bottleneck in prior work, Tiny ORAM is the first hardware ORAM design to support arbitrary block sizes (e.g., 64 Bytes to 4096 Bytes). With a 64 Byte block size, Tiny ORAM can finish an access in 1.4 µs, over 40X faster than the prior-art implementation. Second, through novel algorithmic and engineering-level optimizations, Tiny ORAM reduces the number of symmetric encryption operations by ~ 3X compared to a prior work. Tiny ORAM is also the first design to implement and report real numbers for the cost of symmetric encryption in hardware ORAM constructions. Putting it together, Tiny ORAM requires 18381 (5%) LUTs and 146 (13%) Block RAM on a Xilinx XC7VX485T FPGA, including the cost of encryption
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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DOI of Published Version
http://fccm.org/2015/programme.html#programme
